1. Field of the Invention
The present invention relates to a process for forming the device isolation structure of an integrated circuit (IC). More particularly, the present invention relates to a process for forming a shallow trench isolation (STI) structure.
2. Description of the Related Art
A complete integrated circuit usually consists of millions of metal-oxide-semiconductor (MOS) transistors. To prevent any two neighbouring transistors from short-circuiting, some isolating structures need to be formed. Conventionally, a field oxide (FOX) layer is formed around devices by local oxidation (LOCOS). However, due to the many side effects related to the use of an oxide layer such as internal stress and bird's beak encroachment problem, field oxide isolation has been gradually replaced by shallow trench isolation (STI) structures. In fact, as the critical dimensions (CDs) of devices continues to decrease reaching the deep submicron range, STI structures become the principle means of isolating MOS transistors.
FIGS. 1A through 1E are schematic cross-sectional views showing a process for forming a STI structure according to the prior art. In FIG. 1A, a semiconductor substrate 10 is provided, and a pad oxide layer 12 and a mask layer 14 are subsequently formed thereon. The pad oxide layer 12 is formed by thermal oxidation.
As shown in FIG. 1B, a conventional photolithography and etching process is performed to define the pad oxide layer 12 and the mask layer 14 into a pad oxide layer 12a and a mask layer 14a and to form a shallow trench 15 in the substrate 10. Then, a thermal oxidation process is performed to form a liner oxide layer 16.
As shown in FIG. 1C, an oxide layer 18 is formed by high density plasma chemical vapor deposition (HDPCVD) to cover the substrate 10 and to fill the trench 15. However, the oxide layer 18 formed by the HDPCVD has a peak profile comprising steep peaks 18a. Thus, when a subsequent chemical mechanical polishing is performed to planarize the oxide layer 18, the steep peak 18a encounters a high moment induced by a shear force during the chemical mechanical polishing. As a result, the portion 18b (the shaded part) of the oxide layer 18 in the trench 15 can be pulled out and a defect 19 results, as shown in FIG. 1D. In addition, the pulled-out portion 18b can become particles on the surface of the wafer while performing the chemical mechanical polishing; these particles can damage the surface of the wafer.
Referring to FIG. 1E, the mask layer 14a and the pad oxide layer 12a are removed by wet etching to complete shallow trench isolation structures. However, if the defect 19 exists, there is no isolation structure in some shallow trenches. This lack of isolation structure will seriously affect the operation of the device.